Why is the synthesis result of my Verilog HDL struct signal incorrect?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.1 and earlier, you may see the synthesis result is incorrect when the instantiated variable name of a structure is the same as one of its members.

For example, in the structure definition below, when the design uses in.data, it is synthesized as in.data.data, which is the element of the structure. This means the bit width is 256 bits when it should be 258 bits i.e. 1 bit sop, 1 bit eop and 256 bits data.

interface test #(parameter WIDTH=256) ();
typedef struct packed {
logic sop;
logic eop;
logic [WIDTH-1:0]    data;
} data_t;
data_t data; 
endinterface

......

test #(.WIDTH(256)) in();

assign dout = in.data;

......

To work around this problem, do not use the same name for the structure as one if it's members.

This problem has been fixed beginning with the Intel® Quartus® Prime Pro Edition Software v21.2.