Article ID: 000087700 Content Type: Errata Last Reviewed: 04/18/2022

Why is the o_rx_pcs_fully_aligned signal not asserted in my F-Tile Ethernet Intel® FPGA Hard IP simulation when IEEE 1588 PTP and FEC are enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • OS Independent family

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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.2, the F-Tile Ethernet Intel® FPGA Hard IP does not configure the simulation environment correctly when the IEEE 1588 PTP setting is enabled and the FEC mode setting is configured to any other value different than 'None'. As a result, the o_rx_pcs_fully_aligned signal is not asserted and the simulation is unable to complete the RX reset sequence.

    Resolution

    To work around this problem in the Intel Quartus Prime Pro Edition Software v21.2, follow these steps:

    1. Add the following elaboration option to your simulation script:
      +define+SKIP_SIM_MODEL_LOG2_MRK
    2. Define the following hierarchical path to the F-Tile Ethernet Intel FPGA Hard IP instance in the simulation testbench:
      `define QUARTUS_TOP_LEVEL_ENTITY_INSTANCE_PATH <Quartus_project_name>__tiles.z1577a_<tileid>

      a. As an example, refer to the following hierarchical path: eth_f_hw__tiles.z1577a_x0_y166_n0

      b. The <tileid> location can be found in the filename of the associated generated file, <Quartus_project_name>__z1577a_<tileid>.mif, that can be found in your project folder after executing the 'Support-Logic Generation' step in the Intel Quartus Prime Pro Edition Software.

      c. As an alternative, Chip Planner can be used to find the placement location of the F-Tile Ethernet Intel FPGA Hard IP instance. This procedure requires the execution of Fitter 'place' step before opening the Chip Planner.

    3. Define the LOG2_MRK parameter value in the simulation testbench.

    a. For 25G and 100G F-Tile Ethernet Intel FPGA Hard IP configurations, add the following parameter definition in your testbench:
        defparam `QUARTUS_TOP_LEVEL_ENTITY_INSTANCE_PATH.z1577a.z1577a_inst.u_e400g_top.u_e400g_lphy.LOG2_MRK = 5;

    b. For 50G, 200G and 400G F-Tile Ethernet Intel FPGA Hard IP configurations, add the following parameter definition in your testbench:
        defparam `QUARTUS_TOP_LEVEL_ENTITY_INSTANCE_PATH.z1577a.z1577a_inst.u_e400g_top.u_e400g_lphy.LOG2_MRK = 6;

     

    Note 1:

    For an example of how to implement this workaround, refer to the F-Tile Ethernet Intel Hard IP with IEEE 1588 PTP + FEC Simulation Design Example. The changes described in this workaround can be found in the following files:

    VCS* and VCS MX* simulation script can be found in the following path:

    <design_example_dir>/example_testbench/run_vcs.sh

    ModelSim* and Questa* simulation script can be found in the following path:

    <design_example_dir>/example_testbench/run_vsim.do

    Simulation testbench file can be found in the following path:

    <design_example_dir>/example_testbench/basic_avl_tb_top.sv

    Quartus generated <Quartus_project_name>__z1577a_<tileid>.mif file can be found in the following path:

    <design_example_dir>/hardware_test_design/<Quartus_project_name>__z1577a_<tileid>.mif

     

    The F-Tile Ethernet Intel FPGA Hard IP with IEEE 1588 PTP design example, by default, sets the target <tileid> to x0_y0_n0 in the simulation testbench. In the system design where Tile x0_y0_n0 does not exist or is not the selected Tile, the <tileid> value defined in the testbench has to be modified manually.

     

    Note 2:

    The default value of parameter LOG2_MRK is set to 4 for F-Tile Ethernet Intel FPGA Hard IP variants without IEEE 1588 PTP and FEC enabled.

    The Intel Quartus Prime Pro Edition Software v21.2 only supports a single LOG2_MRK parameter value for an entire F-Tile. When working with a design with multiple instances of the F-Tile Ethernet Intel FPGA Hard IP that require different LOG2_MRK values, placed on a single F-Tile, the simulation will need to be repeated for each LOG2_MRK value capturing the results of the F-Tile Ethernet Intel FPGA Hard IP instances to which LOG2_MRK parameter has been set correctly.

    F-Tile Ethernet Intel FPGA Hard IP instances with the wrong LOG2_MRK parameter value will not work as expected.

     

    Note 3:

    For simulating a multi-tile system design, make sure step 2 and 3 of the workaround is implemented only for the Tile associated to F-Tile Ethernet Intel FPGA Hard IP(s) with IEEE 1588 PTP and FEC enabled.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 22.1.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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