Article ID: 000087686 Content Type: Troubleshooting Last Reviewed: 04/18/2022

Why does simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* example design testbench not include a DMA process?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* example design testbench DMA transactions are not processed.

    Resolution

    In current versions of the Intel® Quartus® Prime Design Software, to correctly simulate DMA processes, modify the 'apps_type_hwtcl' parameter from '3' to '6' within the 'altpcie_a10_tbed_hwtcl' module instantiation in the file 'dut_pcie_tb_ip.v'.

     

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA

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