Article ID: 000087685 Content Type: Troubleshooting Last Reviewed: 01/03/2023

Why doesn't the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express reconfiguration interface access the configuration space registers?

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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Description

For the application logic to access the configuration space registers, use the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express with TLP BYPASS mode, Hard IP reconfiguration interface.

The Hard IP reconfiguration interface cannot be used when the debug toolkit is enabled.

 

Resolution

Ensure that the debug toolkit option is disabled when using the Hard IP reconfiguration interface.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.1.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel® Stratix® 10 DX FPGA

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