Article ID: 000087684 Content Type: Troubleshooting Last Reviewed: 10/06/2021

How can the user logic RTL obtain the bus number and device number for the Intel® Arria® 10 and the Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express*?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The user logic needs to obtain the bus number and device number to correctly generate TLPs, but the bus number and device number are not output from the Intel® Arria® 10 and the Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express*.

    Resolution

    To ascertain the bus number and device number the user logic RTL should read from the cfg_busdev register using the transaction layer configuration space signals. 

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA

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