Error: essai.xcvr_fpll_a10_0: Unable to compute a valid reference clock frequency given desired output frequency, selected pma width and mcbg clock division factor. Your selection of Bandwidth setting may also contribute to this issue.

You may see this error in the Intel® Quartus® Prime Software when implementing a transceiver (XCVR) fractional PLL (fPLL) in Intel® Arria® 10 devices with both Enable downstream cascaded PLL and Operation Mode set to Feedback Compensation Bonding in the fPLL  intellectual property (IP) GUI.

To avoid this error, refer to the Intel® Arria® 10 Device Datasheet and ensure that the input frequency of the fPLL is within the minimum and maximum fCASC_PFD specification (Table 30) and the output frequency is equal to or above the Supported Output Frequency (Table 19).