Article ID: 000087550 Content Type: Troubleshooting Last Reviewed: 10/06/2021

Why does my timing degrade after implementing Distributed Sector Level based clock gating?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Clock Control Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Distributed Sector Level based clock gating  in Intel® Stratix® 10 or Intel® Agilex™ devices results in a Hyper-Retiming restriction for any paths crossing from one clock sector into another, which can result in performance degradation. Distributed Sector Level based clock gating is therefore not recommended for high frequency clock domains or for large designs, which are implemented across multiple clock sectors and rely on Hyper-Retiming.

    Resolution

    This Hyper-Retiming restriction is scheduled to be removed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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