Article ID: 000087546 Content Type: Errata Last Reviewed: 12/07/2024

Why doesn't the HDMI FPGA Sink IP assert the SCDC CED_Update register flag when a character error is detected in the HDMI Sink data channel?

Environment

    Intel® Quartus® Prime Pro Edition
    HDMI
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Critical Issue

Description

Due to a problem in the Quartus® Prime Pro Edition Software v21.2 and earlier, the HDMI FPGA Sink IP core does not assert the SCDC CED_Update register flag when a character error is detected in the high definition media interface (HDMI) sink intellectual property (IP) data channel. This causes the HDMI source IP to read back an incorrect status update from the HDMI sink IP.

 

 

Resolution

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

Related Products

This article applies to 3 products

Intel® Cyclone® 10 GX FPGA
Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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