Article ID: 000087203 Content Type: Troubleshooting Last Reviewed: 08/19/2013

Frequency of coreclkout Reported Incorrectly for Stratix V Hard IP for PCI Express IP Core when the ATX PLL is Used

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The frequency of coreclkout is reported incorrectly for the Stratix V Hard IP for PCI Express IP Core when the ATX PLL is used in Gen1 devices. The Quartus II software reports a frequency for coreclkout that is one half the actual frequency.

    Resolution

    The workaround is to add the following Synopsys Design Constraint (SDC) for coreclkout:

    create_clock -period <half of the Timequest-reported period> [get_pins {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}]

    For example, if TimeQuest reports a 16 ns clock, the SDC is:

    create_clock -period 8.000 [get_pins {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}]

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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