Article ID: 000087194 Content Type: Error Messages Last Reviewed: 07/14/2021

Error (20834): When you enable the CvP setting, you must make sure design is CvP capable.

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Agilex™ I-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to an enhancement in the Intel® Quartus® Prime Pro Edition software version 21.2, the error message shown above will be seen during compilation if the Configuration via Protocol (CvP) CvP Settings in Device and Pin Options is set to “Initialization and Update” but the option “Enable_CvP (Intel_VSEC)” is not checked in the Intel® FPGA F-Tile Avalon® Streaming IP for PCI Express*, R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* or in the P-Tile Intel® FPGA IP for PCI Express* core.

    Resolution

    To work around this problem, enable the following settings to use the CvP feature:

    • Set CvP Settings to “Initialization and update” in Device and Pin options.
    • Enable the option “Enable CVP (Intel VSEC)” in the Intel® FPGA F-Tile Avalon® Streaming IP for PCI Express*, R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* or in the P-Tile Intel® FPGA IP for PCI Express* core.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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