Critical Issue
According to the RapidIO II MegaCore Function User Guide,
in the table that lists the calculations for burstcount and byteenable on
the Avalon-MM interface for a RapidIO write transaction with wrsize in
the range of 4’b1100 to 4’b1111, the value of the RapidIO field address[0] affects
the IP core output burst count on the Avalon-MM interface if the
payload size is not a multiple of 16 bytes. However, this information
is incorrect. The burstcount value for a write transaction with
a payload size that is not a multiple of 16 bytes does not vary
with the value of the RapidIO transaction address[0] bit.
In all such cases, the value of burstcount is the number
of 8-byte words in the packet payload, divided by two, and rounded
up.
This issue has no workaround. Ensure that you understand the
expected burstcount value in this case according to
the description above and not according to Table 4-8: Avalon-MM
I/O Master Write Transaction Burstcount and Byteenable II in the
RapidIO II MegaCore Function User Guide.
This issue is fixed in version 14.0 of the RapidIO II MegaCore Function User Guide.