Article ID: 000087189 Content Type: Troubleshooting Last Reviewed: 07/07/2014

Cyclone V Hard IP for PCI Express IP Core Transmits Incorrect TS1 During Link Training

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Cyclone V Hard IP for PCI Express IP Core may send out corrupted TS1 during link training. After sending out corrupted TS1s, the Cyclone V Hard IP for PCI Express IP Core enters the Polling.Config state. However, the link partner can only proceed to the Polling.Active state, causing link training to fail.

    Resolution

    This issue is fixed in version 13.1 Update 1 of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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