Article ID: 000087186 Content Type: Troubleshooting Last Reviewed: 06/15/2016

Why do I see an error accessing my FPGA IP on my Arria 10 SoC Design?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Arria® 10 U-Boot bootloader in SoC EDS version 15.1.2 and earlier, there is a NOC timeout that is erroneously left enabled by the reset_assert_all_bridges function. This timeout can be reached if IP in the FPGA is slow to respond, resulting in an access error.

    Resolution

    This problem is scheduled to be fixed in the next release of SOC EDS. There is a patch available to address this issue with previous releases here:  https://github.com/altera-opensource/u-boot-socfpga

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 SX SoC FPGA

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