Critical Issue
Description
The RapidIO II IP core Logical/Transport Layer Error
Detect CSR (offset 0x308) should indicate detected errors
only for error types that are enabled in the Logical/Transport
Layer Error Enable CSR (offset 0x20C). However, the Logical/Transport
Layer Error Detect CSR detects errors irrespective of the corresponding
enable settings.
In addition, the Logical/Transport Layer Error Detect
CSR should not support the clearing of individual bits. However,
user logic can clear the register bits individually.
Resolution
This issue has no workaround.
This issue is fixed in version 14.0 of the RapidIO II MegaCore function.