Article ID: 000087146 Content Type: Troubleshooting Last Reviewed: 11/24/2011

DDR2 and DDR3 SDRAM Controller with UniPHY User Guide Contains Incorrect Clock Information

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In the user guide, table 6-1 contains incorrect clock phase information for pll_mem_clk and pll_write_clk.Also, table 6-2 is inapplicable and should be ignored.

    Resolution

    The correct phase for pll_mem_clk is 0° for interfaces with the Leveling Interface� Mode set to Leveling, and -45° for interfaces with Leveling Interface Mode set to Nonleveling.�The correct phase for pll_write_clk is 90° for interfaces with the Leveling Interface� Mode set to Leveling, and -135° for interfaces with Leveling Interface Mode set to Non-leveling.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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