DDR2 and DDR3 SDRAM Controller with UniPHY User Guide Contains Incorrect Clock Information

In the user guide, table 6-1 contains incorrect clock phase information for pll_mem_clk and pll_write_clk.Also, table 6-2 is inapplicable and should be ignored.

The correct phase for pll_mem_clk is 0° for interfaces with the Leveling Interface� Mode set to Leveling, and -45° for interfaces with Leveling Interface Mode set to Nonleveling.�The correct phase for pll_write_clk is 90° for interfaces with the Leveling Interface� Mode set to Leveling, and -135° for interfaces with Leveling Interface Mode set to Non-leveling.