40-100GbE MAC and PHY IP Core MegaCore Function rx_recovered_clk Signal is Missing from Top Level Interface

If you turn on Synchronous Ethernet support in the 40-100GbE parameter editor with the Enable SyncE support parameter, the IP core is configured with two input reference clocks, one reference clock for the RX CDR PLL and one reference clock for the TX PLL. In addition, the RX recovered clock should be an IP core external signal. However, the RX recovered clock signal is not visible at the top level of the IP core.

This issue has no workaround.

This issue is fixed in version 14.0 of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.