Description
Due to a problem in the Quartus® II Web Edition software version 13.0SP1, you may see this internal error when running the EDA Netlist Writer to generate an output netlist in SystemVerilog HDL format.
Resolution
To avoid this problem, change the format for output netlist to Verilog HDL or VHDL.
To change the output format go to Assignments in Quartus II menu and select Settings . Select EDA Tool Settings and select Simulation. Choose Verilog HDL or VHDL output format instead of SystemVerilog HDL.
This problem is scheduled to be fixed in a future version of the Quartus II Web Edition software.