Article ID: 000087119 Content Type: Troubleshooting Last Reviewed: 01/01/2015

50G Interlaken MegaCore Function User Guide Provides Insufficient Information to Connect Arria 10 TX PLL

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    According to the 50G Interlaken MegaCore Function User Guide, user logic should drive the tx_pll_locked input signal to an Arria 10 100G Interlaken IP core with the logical AND of the pll_locked output signals of the Arria 10 TX PLL IP cores. However, this information is incomplete. The input signals to the logical AND should also include the inverse of each TX PLL pll_cal_busy signal.

    For illustration in the case of a single external TX PLL, refer to Figure 5-3, Arria 10 PLL to Arria 10 100G Interlaken MegaCore Function Connection Diagram, in the "Migrating 100G Interlaken IP Core from Stratix V to Arria 10 Devices" chapter of the Arria 10 Migration Guide.

    Resolution

    This issue has no workaround. Ensure you connect the Arria 10 external TX PLLs to your 50G Interlaken IP core according to the instructions in this erratum.

    This issue is fixed in version 14.1 of the 50G Interlaken MegaCore Function User Guide.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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