Article ID: 000087118 Content Type: Troubleshooting Last Reviewed: 11/23/2011

Timing-Related Warning Messages for QDR II and QDR II SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY When Sharing PLLs on Stratix V Devices

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When instantiating a design in PLL/DLL slave mode on a Stratix V device, the TimeQuest Timing Analyzer may display warning messages similar to the following:

    Warning: Ignored filter at slave_report_timing_core.tcl(176): slave_inst0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads| dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|thechain|clkin could not be matched with a keeper or register or port or pin or cell or net Warning: Command get_path failed.
    Resolution

    This issue has no workaround. The warning messages can be safely ignored; however, do not rely on the accuracy of the resulting timing analysis.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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