Starting with the Quartus Prime software version 16.0, you may see this error message during the Fitter stage when the design instantiates an Arria 10 External Memory Interface (EMIF) IP.
This error occurs if you configure the EMIF IP such that the "PLL reference clock I/O standard" setting uses the "LVDS with On-Chip Termination" value and your .qsf file explicitly overrides the PLL reference clock pin to use a non-LVDS I/O standard (e.g. 1.2-V).
The error occurs because EMIF IP explicitly enables "Differential" input termination for the PLL reference clock in the IP\'s .qip file if the "LVDS with On-Chip Termination" setting is used. Differential input termination is not supported by non-LVDS I/O standard.
To resolve this error, you can do one of the following:
- Add a new assignment in the .qsf file to explicitly disable input termination for the PLL reference clock. For example:
set_instance_assignment -name INPUT_TERMINATION OFF -to <name of PLL reference clock pin>
- Re-configure and re-generate the IP such that you specify the desired single-ended I/O standard (e.g. 1.2-V) for the PLL reference clock I/O standard.
- If you actually intend to use the LVDS I/O standard for the PLL reference clock (which is recommended in order to improve noise rejection compared to single-ended I/O standard), simply remove the assignment in your .qsf file that sets the PLL reference clock I/O standard.