CvP update stress tests might fail when a Stratix V GX Hard IP for PCI Express IP Core design also includes the Transceiver Reconfiguration Controller IP Core. This hardware issue does not affect CvP initialization.
For some systems, removing the Transceiver Reconfiguration
Controller IP Core from the system design and tying the Avalon Memory-Mapped
interface_sel signal for each channel or
PLL to 1’b1 resolves this issue. The interface_sel signal is
each channel or PLL. However, this workaround prevents you from
assigning different protocols to the 6 channels in a transceiver
bank. A comprehensive solution is under investigation.