Article ID: 000087079 Content Type: Troubleshooting Last Reviewed: 05/18/2013

Possible Enumeration Failure for Stratix V Hard IP for PCI Express Gen3 x8

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Gen 3 x8 variants of the Stratix V GX Hard IP for PCI Express IP Core may fail during enumeration when the adaptive equalization (AEQ) is active during the LTSSM speed change state.

    Resolution

    This issue is fixed in version 12.1 SP1 of the Hard IP for PCI Express IP Core.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.