Article ID: 000087038 Content Type: Troubleshooting Last Reviewed: 10/28/2013

Infrequent Host Replay Timer Timeout for Stratix V Hard IP for PCI Express IP Core

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Infrequent host replay timer timeouts can occur, because the Stratix V Hard IP for PCI Express IP Core infrequently skips transmitting ACK DLLP for a given received packet. This issue only occurs when the Stratix V Hard IP for PCI Express IP Core is receiving a discrete stream of packets with large time lags between packets. This issue does not occur when receiving a continuous stream of packets.

    This issue does not affect functionality because the replay timer mechanism ensures data retransmission.This issue does not affect throughput due its very infrequent occurrence.

    Resolution

    No workaround is available.

    Related Products

    This article applies to 2 products

    Stratix® V FPGAs
    Arria® V FPGAs and SoC FPGAs

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