Article ID: 000087033 Content Type: Troubleshooting Last Reviewed: 09/18/2013

PCIe Gen2 Link Training Error When Using Hard Reset Controller

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    An intermittent PCIe Gen2 Hard IP link-up issue may occur in Quartus II version 13.0SP1 and earlier. When using the hard reset controller in a Gen2 native configuration, the Stratix V Hard IP for PCI Express MegaCore function may incorrectly transmit at 5 Gbps instead of the 2.5 Gbps data rate during link training.

    Resolution

    For Gen2 configurations that do not use Configuration via Protocol (CvP), follow the instructions in Knowledge Base Solution for a workaround. For CvP Gen2 configurations, contact mySupport.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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