Article ID: 000087018 Content Type: Troubleshooting Last Reviewed: 04/15/2013

Errata - Known Arria V timing model issues in Quartus II software version 12.1 SP1


  • Quartus® II Subscription Edition

    Critical Issue


    For designs that target Arria® V devices in the Quartus® II software version 12.1 SP1, there are known issues with some timing delays.

    Refer back to this solution for up-to-date workaround information and any newly reported issues.

    Missing delay between HSSI output clock and fPLL refclk input

    A clock path is missing a delay in designs targeting Arria V devices when the following circumstances are all true:

    1. There is a connection between the HSSI clock output and an fPLL refclk input
    2. The connection includes an IQTXRXCLK routing resource
    3. The connection does not go through Global, Regional, or Periphery Clock Networks

    None of the intellectual property cores distributed by Altera use this clock connection.


    This solution will be updated at a future date with more details about how to determine if your design is affected, and how to work around the problem.

    Related Products

    This article applies to 5 products

    Arria® V GT FPGA
    Arria® V GX FPGA
    Arria® V GZ FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA



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