Article ID: 000087014 Content Type: Troubleshooting Last Reviewed: 01/17/2013

Stratix V Hard IP for PCI Express Issue If rx_st_mask Toggles when rx_st_ready Is 0

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    The Stratix V Hard IP for PCI Express IP Core may send invalid data if rx_st_mask toggles while rx_st_ready is 0. The Hard IP may not recover once this event occurs.

    Resolution

    There is not a workaround. Altera recommends that you disable the rx_st_mask signal for Stratix V devices.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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