Article ID: 000087013 Content Type: Troubleshooting Last Reviewed: 06/18/2012

Deep Power Down Issue With LPDDR2 Interfaces on Cyclone V Devices Using Hard Processor System

Environment

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    Critical Issue

    Description

    This problem affects LPDDR2 products.

    In LPDDR2 interfaces targeting Cyclone V devices using the hard processor system (HPS), if the auto power down (APD) feature is enabled and has been triggered by lack of activity, an explicit user request to enter deep power down (DPD) mode may not be recognized. This problem occurs because the system ignores explicit DPD requests when it is already in APD-triggered DPD mode.

    Resolution

    The workaround for this issue is to ensure that the HPS memory controller is not already in DPD mode as a result of the APD feature. You can cause the memory controller to exit APD mode by issuing a dummy write command to any address.

    The recommended procedure is as follows:

    1. Issue the deep power down request.
    2. Issue a write command to any memory address.

    This issue will not be fixed.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs

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