RapidIO II IP Core Does Not Support VHDL Models

The RapidIO II IP core does not support VHDL models. If you generate a RapidIO II IP core in VHDL, it cannot compile successfully.

The RapidIO II MegaCore Function User Guide claims you can specify that Qsys should generate a VHDL simulation model. However, for a Qsys system that includes a RapidIO II IP core, this option is not viable. This statement in the user guide is in error.

To avoid this issue, generate your RapidIO II IP core and Qsys functional simulation models and test bench in Verilog HDL.

This issue is fixed in version 13.1 of the RapidIO II IP core.