Article ID: 000086988 Content Type: Troubleshooting Last Reviewed: 12/03/2014

Why are some DDR4 signals unconstrained in TimeQuest?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see the following signals show up as unconstrained input and output ports in TimeQuest:

    mem_alert_n

    mem_dbi_n

    mem_ck/mem_ck_n

    mem_dqs_n

    These signals should have false path assignments.

    Resolution

    Add the following assignments to the DDR4 SDC file under the FALSE PATH CONSTRAINTS section:

        set_false_path -from [get_ports {*alert_n*}]
        set_false_path -from [get_ports {*dbi_n*}]
        set_false_path -to [get_ports {*dbi_n*}]
        set_false_path -to [get_ports {*mem_ck*}]
        set_false_path -to [get_ports {*mem_ck_n*}]
        set_false_path -to [get_ports {*mem_dqs_n*}]

    This issue will be fixed in a future version of the Quartus® II software.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 GX FPGA

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