Article ID: 000086983 Content Type: Troubleshooting Last Reviewed: 07/09/2014

Stratix V Hard IP for PCI Express Qsys Example Design Shows Incorrect Connection for Transceiver Reconfiguration Controller Reset

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

The following Qsys example designs for the Stratix V Hard IP for PCI Express IP Core shows two reset outputs driving the reset input to the Transceiver Reconfiguration Controller mgmt_rst_reset port: Gen1 x4, Gen1 x8, Gen2 x1, and Gen2 x4.

Resolution

This is issue is fixed in version 13.1 Update 1 of the Quartus II software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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