Article ID: 000086983 Content Type: Troubleshooting Last Reviewed: 07/09/2014

Stratix V Hard IP for PCI Express Qsys Example Design Shows Incorrect Connection for Transceiver Reconfiguration Controller Reset

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The following Qsys example designs for the Stratix V Hard IP for PCI Express IP Core shows two reset outputs driving the reset input to the Transceiver Reconfiguration Controller mgmt_rst_reset port: Gen1 x4, Gen1 x8, Gen2 x1, and Gen2 x4.

    Resolution

    This is issue is fixed in version 13.1 Update 1 of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.