Article ID: 000086973 Content Type: Error Messages Last Reviewed: 09/11/2012

Warning: PLL cross checking found inconsistent PLL clock settings.

Environment

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Description

The Quartus® II software version 9.1 SP1 and later may generate the following warnings, when a transceiver PCS is used in designs targeting Stratix® IV devices:

Warning: PLL cross checking found inconsistent PLL clock settings:
        Warning: Clock: <instance name>|receive_pcs0|clkout does not match the master clock period requirement: 0.001
        Warning: Clock: <instance name>|transmit_pcs0|clkout does not match the matser clock period requirement: 0.001

These warnings on transmit and receive PCS clock outputs can safely be ignored because the clock period for these clocks is automatically set correctly in the TimeQuest Timing Analyzer.

This problem is currently scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 2 products

Stratix® IV GX FPGA
Stratix® IV GT FPGA

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