Article ID: 000086961 Content Type: Error Messages Last Reviewed: 02/26/2016

Warning (332060): Node: *inst_twentynm_hssi_common_pcs_pma_interface~pma_hclk.reg was determined to be a clock but was found without an associated clock assignment.

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the timing constraints for the Arria® 10 Hard IP for PCI Express® you may encounter the following warning in TimeQuest.

    Node: <ip instance>|altpcie_a10_hip_hwtcl:pcie_1x|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g1x1:g_xcvr.g_phy_g1x1.phy_g1x1|altera_xcvr_native_a10:phy_g1x1|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es2:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es2:inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_hclk.reg was determined to be a clock but was found without an associated clock assignment.

    Resolution

    Apply the following timing constraint to correctly constrain this clock.

    create_generated_clock -name {pcie_1x|pma_hclk_by2} -source [get_pins -compatibility_mode {*altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g1g2x1.fpll_g1g2x1|fpll_g1g2x1|fpll_refclk_select_inst|refclk}] -duty_cycle 50.000 -multiply_by 5 -divide_by 2 [get_pins -compatibility_mode {*altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g1x1.phy_g1x1|phy_g1x1|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}]

    This problem has been fixed in software version 15.0 and later of the Quartus® software.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 GT FPGA

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