Why does my Arria 10 SoC industrial grade device fail to boot at low temperature?

Certain Hard Processor System (HPS) PLL clock output frequencies require a specific programming setup sequence to ramp the PLL frequency gradually in Arria 10 SoC industrial grade devices at -40degreesC, otherwise the HPS may fail to boot.

To workaround this issue in SoC EDS software version 16.0, download the patch below and follow the instructions in the readme.

Download the SoC EDS software version 16.0 Patch 002soc for Linux(.run)

Download the Readme for SoC EDS software version 16.0 Patch 002soc for Linux(.txt)

The corresponding patch for socfpga UEFI is available in the rel_socfpga_arria10_soceds_16.0 tag of the socfpga_udk2015 branch from the github repository:
https://github.com/altera-opensource/uefi-socfpga. 

This problem is scheduled to be fixed in a future version of the SoC EDS software.