Article ID: 000086943 Content Type: Error Messages Last Reviewed: 12/07/2024

Internal Error: Programmable pre-emphasis option is set to 1 for pin dut_mem_mem_par(0)~pad, but setting is not supported by I/O standard SSTL-12 with Slew Rate 0

Environment

  • Intel® Quartus® Prime Standard Edition
  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see an error similar to the one shown below when compiling the DDR4 IP in the Quartus® Prime Software versions 18.0 and 18.0.1.

     Internal Error: Programmable pre-emphasis option is set to 1 for pin <signal_name>~pad, but setting is not supported by I/O standard SSTL-12 with Slew Rate 0

    The <signal_name> is one of the DDR4 address/command signals.

     

    Resolution

    In the Quartus® Prime project .QSF file, enter the following assignment:

    set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS 0 -to <signal_name>

    Add a similar assignment for each affected DDR4 signal.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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