Article ID: 000086938 Content Type: Troubleshooting Last Reviewed: 11/28/2018

Why doesn't the Intel® Arria® 10 and the Intel Stratix® 10 QDR-IV IP issue burst accesses? 

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime software versions 18.1 and earlier, the Intel® Stratix® 10 and the Intel Arria® 10 QDR-IV IP can only support a burst length of one at the Avalon Memory-Mapped interface. This is to avoid the QDR-IV banking policy across Port A and Port B for better bus efficiency.

    Resolution

    This problem is planned to be fixed in a future version of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs

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