Article ID: 000086935 Content Type: Error Messages Last Reviewed: 12/07/2024

Warning: Ignored Maximum Fan-Out assignment

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When compiling a Stratix® 10 EMIF IP example design in the Quartus® Prime Software Pro version 18.1, you may see a similar warning as shown below.

Warning: Ignored Maximum Fan-Out logic option for node "ed_synth_inst|dut|dut|arch|arch_inst|hmc_avl_if_inst|amm.ready_0_hyper_regs.amm_ready_0_r1~SynDup"

Note that the hierarchy path of the amm_ready_0_r1~SynDup signal may differ for a given design.

This warning doesn’t affect design functionality and can be ignored.

Resolution

This issue has been fixed in Quartus® version 19.1 and onward. 

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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