Article ID: 000086930 Content Type: Troubleshooting Last Reviewed: 01/18/2023

Why does the Avalon® controller in the design example generate the wrong write address to the Intel® Arria®10 PHYLite IP which causes the dynamic reconfiguration to fail?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The wrong address offset is generated when using the Intel® Arria® 10 PHYLite design example with an Avalon® controller.

     

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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