Article ID: 000086929 Content Type: Troubleshooting Last Reviewed: 06/05/2018

Why doesn't the Intel® Arria® 10 or the Intel Stratix® 10 DQ/DQS x4 configuration follow the pin-out placement documentation and the DQ/DQS Pins view in the Intel Quartus® Prime Pin Planner?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When the EMIF IP is configured as DDR3 or DDR4 with x4 DQ/DQS groups, the Quartus® Prime may automatically assign DQ pins to pin locations that don't follow the x4 DQ/DQS groups defined in the device pin-out files.

    Resolution

    In the Intel® Arria® 10 or Intel Stratix® 10 I/O architecture for x4 DQ/DQS configuration, it is legal to assign a DQ pin to any DQ I/O location within a x12 I/O lane.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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