Article ID: 000086924 Content Type: Troubleshooting Last Reviewed: 08/29/2017

Why fitter error with different voltage level on Stratix 10 3V IO bank?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When constrainted IO with different IO standard in different 3V IO bank, fitter failed like the following error message.  


     Error (175020): The Fitter cannot place logic pin in region (0, 12) to (0, 14), to which it is constrained, because there are no valid locations in the region for logic of this type.
     Error (19261): Signal xxx has been constrained to a location that is a dual purpose pin that can be used by the PCIe HIP as nPERST.  If using the signal as nPERST, please select a 3V IO_STANDARD.  If you are not using PCIe and are intentionally trying to use a non-3V standard on this pin, please add 'set_instance_assignment -name USE_AS_3V_GPIO ON -to local_rstn' to your QSF file. Otherwise, you can move this signal to another location. (1 location affected)

    Resolution

    All 3V IO banks should be powered at the same voltage for Stratix 10.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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