How can I enable external trace on the Arria 10 SOC development kit?

To enable external trace via MICTOR connectors J43 and J20 specific switch settings are required on the Arria® 10 SOC development kit.  

The Arria 10 SOC Goldern Hardware Reference Design (GHRD) is configured to enable 4bit trace by default,  and can be auto-configured to enable 16bit trace. 

Note: The Max® V device must be removed from the JTAG chain to allow the Arm® DS-5 debugger to connect to the Arria 10 Hard Processor Subsystem.

To enable early trace (4 bit) via MICTOR connector J43:

4 bit external trace via MICTOR connector (J43) is enabled in the default configuration of the Arria 10 Goldern Hardware Reference Design (GHRD).

Development kit settings for 4 bit trace via MICTOR conector J43:

• SW3 bits 678 must be set to on, on, on. This routes JTAG to J43
• SW3 bit 2 must be set to on.  This takes the Max V out of the JTAG chain.

To enable fast trace (16 bit) via MICTOR connector J20:

The GHRD design must be re-built to enable fast trace.

1. Edit the Makefile to set HPS_ENABLE_16BIT_TRACE := 1
2. Re-build the design by running  make sof from a SoC EDS command shell.

Development kit settings for 16 bit trace via MICTOR conector J20:

• SW3 bits 6,7,8 must be set to off, on, on.   This routes JTAG to J20
• SW3 bit 2 must be set to on.  This takes the max V out of the chain.