Article ID: 000086915 Content Type: Troubleshooting Last Reviewed: 10/17/2016

What is the MDIO clock to output data maximum specification for Cyclone V SOC and Arria V SOC devices?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

MDIO clock to output data maximum specification (Td Max) for the HPS Ethernet MAC on Cyclone® V SOC and Arria® V SOC devices is 20ns.

This information is scheduled to be added to a future version of the Cyclone V SOC and Arria V SOC device datasheets.

Related Products

This article applies to 5 products

Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA

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