Article ID: 000086912 Content Type: Troubleshooting Last Reviewed: 04/18/2023

What is the behavior of the traffic generator status signals in the Intel® Arria® 10 and the Intel® Stratix® 10 EMIF IP example design?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Arria® 10 FPGA IP
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
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Description

The traffic_gen_pass signal will go high if there are no bit errors and the test loops for a specific number of cycles.  In the infinite loop test mode, the traffic_gen_pass signal will never go high.

The traffic_gen_fail signal goes high whenever a pnf_per_bit (pnf = pass not fail) signal goes low,  regardless of how many loops the test runs.

The traffic_gen_timeout signal goes high when there is a timeout due to a problem with the traffic generator.

 

Resolution

All traffic generator status signals will remain low if the interface fails calibration.

Related Products

This article applies to 2 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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