Article ID: 000086897 Content Type: Troubleshooting Last Reviewed: 07/26/2018

Why does the Intel® Stratix® 10 MX device fail configuration?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Software version 18.0, an Intel Stratix® 10 MX device will fail configuration when the Universal Interface Block (UIB) PLL reference clock is not running even if there is no HBM2 IP in the project.

    Resolution

    Connect up the UIB PLL reference clock to the Intel Stratix 10 MX device and provide a clock that meets the required specification shown in the Stratix 10 Device family Pin Connection Guidelines

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA

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