Description
Due to a problem in the Intel® Quartus® Prime Pro Software version 18.0, an Intel® Stratix® 10 MX device will fail configuration when the Universal Interface Block (UIB) PLL reference clock is not running even if there is no HBM2 IP in the project.
Resolution
Connect up the UIB PLL reference clock to the Intel Stratix 10 MX device and provide a clock that meets the required specification shown in the Intel® Stratix® 10 Device Family Pin Connection Guidelines.
This problem has been fixed in Intel® Quartus® Prime Pro Edition Software version 18.0.1