Article ID: 000086884 Content Type: Troubleshooting Last Reviewed: 09/12/2019

Why does the frequency generated by the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP is different from the user input frequency?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1 and the Intel® Quartus® Prime Standard Edition software version 18.1 update 1, you may see that the Interface clock frequency, PLL reference clock frequency and VCO clock frequency of the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP generated is different from the user input frequency. When you perform an RTL simulation, you will see that the frequency used is the user input frequency instead of the frequency in the compilation report.

    For example,

    Resolution

    To avoid rounding error in the RTL simulation, frequencies are round up to the nearest even number so that every clock edge is aligned during simulation. However, in the real hardware, the frequency will be the frequency in Compilation Report. 

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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