Why aren’t the System Verilog assertion messages returned when running the Intel® Quartus® Prime Pro Edition Software?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software, System Verilog info/warning/error/fatal assertion messages may not be returned in the Analysis & Synthesis Messages window when you wrap the system task in a function.

To work around this problem, place the system task directly in a module rather than wrapping it in a function. Alternatively, you may convert the operand in the function into a string-literal instead of a string, but converting to a string literal limits the function to fixed-length messages.

This problem is fixed starting with the Intel Quartus Prime Pro Edition software version 20.4.