Article ID: 000086872 Content Type: Troubleshooting Last Reviewed: 08/23/2019

Why do I see max skew timing violations when Signal Tap is enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1, you may encounter max skew violations when compiling project with Signal Tap enabled. These violation occur in designs targeting Intel® Arria® 10 devices because the auto generated timing constraint in intel_signal_tap.sdc over constrain the max delay to 1ns.

     

    Resolution

    To work around this problem, write a set_max_delay constraint as follow to over write the set_max_delay constraint in the auto generated intel_signal_tap.sdc:

    set_max_delay -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_top|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|jtag_acq_clk_xing|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_top|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|jtag_acq_clk_xing|intel_stp_status_bits_cdc_u1|stp_status_bits_out[*]}] 30.000

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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