Article ID: 000086862 Content Type: Troubleshooting Last Reviewed: 06/18/2019

Why are the Output Enable/Disable Times for a bus the minimum value for all bits of the bus?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1, the Output Enable/Disable Times reports the minimum delays instead of displaying the maximum value for bus bits. This problem occurs when targeting Intel® Stratix® 10 devices.  

    Resolution

    To work around this problem, expand the aggregated data bus bits and identify the maximum delay value manually.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.