Article ID: 000086860 Content Type: Troubleshooting Last Reviewed: 01/14/2019

Why do I have functional errors in my Intel® Stratix® 10 design?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1 and earlier, you may see functional errors in your Intel® Stratix® 10 design. This problem occurs when 7 or 8 inputs LUTs are incorrectly optimized during pin rotation.

    Resolution

    To work around this problem download and install the patch for the Intel Quartus Prime Pro edition software version 18.0 Update 1 or 18.1

    Download and install Patch 1.44 for 18.0 Update 1 from the appropriate link below.

    Download and install Patch 0.33 for 18.1 from the appropriate link below.

     

    This problem is fixed beginning with the Intel Quartus Prime Pro Edition software version 18.1 Update 1

    For designs that are already in production, download and run the script lut8_iobuf_qsh_v3.tcl to check if the compiled design is affected by this problem. 

    • Command -> quartus_sh -t lut8_iobuf_qsh_v3.tcl -project <project name> -revision <revision name> -npaths 100 -debug 0 -verbose -check_lutmasks -vo_file simulation/modelsim/<revision name>.vo
    • Output -> lut8check.rpt, iobuf.rpt, paths.csv

    lut8check.rpt reports the LUTs impacted, if this report contains "Found 0 LUTs with potentially incorrect bit settings" then the compiled design is safe. If the design is affected then the LUTs with this problem will be listed in the report.

    iobuf.rpt and paths.csv report the paths that are affected by the timing model changes described in the KDB Is the Intel® Stratix® 10 timing model correct in the Intel® Quartus® Prime Pro Edition software versions 18.0 Update 1 and 18.1?

      

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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