This error may be seen during analysis & synthesis in the Intel® Quartus® Prime Pro Edition Software version 19.3 and earlier and the Intel® Quartus® Prime Standard Edition Software version 19.1 and earlier.
This is due to the Total Memory Size assigned in the On-Chip Memory (RAM or ROM) Intel® FPGA IP (with different widths of dual port access) not being aligned with the Slave S1 and S2 data width, resulting in a non-integer (invalid) FIFO depth.
To avoid this error in the Intel® Quartus® Prime Pro/Standard Edition Software, change the Total Memory Size of On-Chip Memory (RAM or ROM) Intel® FPGA IP to align with the slave S1 and S2 data width.
For example, a Total Memory Size of 19394 bytes divided by 4 bytes (port width of S1/S2) will result in non-integer FIFO depth. Change the Total Memory Size option from 19394 to 19396 will solve the problem.
This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 20.1.