Article ID: 000086833 Content Type: Product Information & Documentation Last Reviewed: 11/27/2024

How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Stratix® 10 DDR4 IP?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
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Description

Due to a problem in the Quartus® Prime Software versions 18.0 and 18.1, a large trace file called iossm_bf_cpu_cpu.tr is generated when you simulate a design containing the Stratix® 10 DDR4 IP.

Resolution

To disable the generation of the iossm_bf_cpu_cpu.tr file, download and install the Quartus® Prime Software version 18.1 patch 0.21.

               > Download the Readme (.txt) for the version 18.1 patch 0.21
               > Download the version 18.1 patch 0.21 for Windows (.exe)
               > Download the version 18.1 patch 0.21 for Linux (.run)

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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